The present invention relates to an advanced control data processing system.
In the advanced control data processing system, an instruction currently executed as well as a certain number of sequence instructions are prefetched from a main storage and buffered in a high speed storage called an instruction buffer, and when the current instruction has been executed the next instruction is read from the instruction buffer for execution. In this manner, the overhead involved in the instruction fetch operation which occurs between instruction executions is reduced.
Since the fetch of instructions from the memory (main storage) to the instruction buffer is usually effected in accordance with the data depth of the memory, that is, eight bytes at a time, data as an operand can be read out as well as the instruction. As the capacity of the instruction buffer increases, the tendency of fetching the data as the operand to the instruction buffer increases. Under such a circumstance, an inconsistency will occur between the memory and the instruction buffer if a preceding instruction calls for a memory store operation to change an instruction or data in the memory, which instruction or data has already been fetched to the instruction buffer.
Such an inconsistency between the memory and the instruction buffer can be resolved by invalidating the entire content of the instruction buffer when the content fetched to the instruction buffer is changed in the memory and fetching instructions (which may include data depending on the data depth of the memory and the capacity of the instruction buffer) included between the address of the currently executed instruction and the address of the changed instruction or data.
However, if a branch instruction is included preceding the changed instruction or data and the branch by that branch instruction succeeds, or if the data, not the instruction, is changed (the data fetched to the instruction is neglected because it is not an instruction), the changed content may not be validly executed as an instruction. In such a case, it is not desirable from a standpoint of efficiency of instruction execution to invalidate the entire content of the instruction buffer including valid instructions and refetch the instructions or data from the memory.
Japanese Patent Application Laid-Open No. 54-82140 (Japanese Patent Publication No. 56-40378) of the present assignee discloses means for preventing the decrease of the efficiency of the instruction execution due to the invalidation of the instruction buffer by suppressing further prefetch if the content prefetched to the instruction buffer is changed in the memory by the memory store operation and invalidating the content of the instruction buffer when the instruction execution proceeds to the changed instruction. In order to detect that the instruction execution has proceeded to the changed instruction, the address for the store operation and the address of the instruction to be executed are compared, and when they are equal it is determined that the instruction execution has proceeded to the changed instruction. However, since the comparison is made only by addresses and hence a minimum unit of the comparison is the data depth (e.g. eight bytes) of the data from the memory, the instruction buffer will be invalidated only if the compare equality is detected for the eight-byte blocks even if the byte position for the store operation and the byte position of the instruction to be executed are not equal. Thus, there still remains a possibility that the instruction buffer is invalidated when the changed content is not validly executed as an instruction.